Disclosed herein are techniques related to precharging an analog-to-digital (DAC) capacitance. For example, DAC capacitances are used in an analog-to-digital converter (ADC). An input of an analog-to-digital converter can form a switched capacitor load. For example, an input of a successive-approximation register analog-to-digital converter (SAR-ADC) captures an analog input voltage signal with either an external sample-and-hold (S/H) device or a sample-and-hold function internal to the SAR-ADC. The SAR-ADC compares the analog input voltage to known fractions of a reference voltage used with the SAR-ADC. The reference voltage determines the full-scale input voltage range of the SAR-ADC.
These days, successive-approximation register analog-to-digital converters use a capacitive, digital-to-analog converter (C-DAC) to successively compare bit combinations and set or clear appropriate bits into a data register. At an input of an SAR-ADC converter, an input signal first ‘sees’ a switch. The switch, when closed, creates a switch resistance in series with a capacitive array connected between a comparator and, selectively, either the input, a reference terminal, or ground. Once the capacitive array acquires the input signal, an input switch opens to disconnect the capacitive array from the input. Now, selectively, at least one DAC capacitance of the capacitive array is connected to the reference terminal. Charge is redistributed among all DAC capacitances. Accordingly, voltage at the comparator input moves. If a voltage at the sampling capacitance is larger than a fraction of the reference voltage as represented by the selected DAC capacitance, then the comparator outputs a 0 level signal, otherwise the comparator outputs a 1 level signal.